Clock feed-through analysis in switched-capacitor integrator transmission gates switches

Author

Shakeri, Majid ; Torkzadeh, Pooya ; Samani, Sahel Shariati

Author_Institution

Natanz Branch, Islamic Azad Univ., Natanz, Iran

fYear

2009

fDate

6-9 May 2009

Firstpage

500

Lastpage

503

Abstract

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18 um CMOS technology in ADS environment show the validity of extracted equations.

Keywords

CMOS digital integrated circuits; circuit simulation; clocks; sigma-delta modulation; switched capacitor networks; ADC; ADS environment; CMOS transmission gates switches; circuit simulations; clock feed-through analysis; clock signal timing model; sigma-delta modulator; signal processing applications; size 0.18 mum; switched-capacitor integrator; CMOS process; CMOS technology; Clocks; Degradation; Delta-sigma modulation; Linearity; Signal processing; Switches; Switching circuits; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, 2009. ECTI-CON 2009. 6th International Conference on

Conference_Location

Pattaya, Chonburi

Print_ISBN

978-1-4244-3387-2

Electronic_ISBN

978-1-4244-3388-9

Type

conf

DOI

10.1109/ECTICON.2009.5137057

Filename

5137057