DocumentCode :
2311927
Title :
ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs
Author :
Banga, Mainak ; Hsiao, Michael S.
Author_Institution :
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
fYear :
2011
fDate :
5-6 June 2011
Firstpage :
18
Lastpage :
23
Abstract :
In this paper, we propose a two-step non-scan design-for-test methodology that can ease detection of an embedded Trojan and simultaneously partially obfuscates a design against Trojan implantations. In the first step, we use Q signals of flip-flops in a circuit to increase the number of reachable states. In the second step, we partition these flip-flops into different groups enhancing the state-space variation. Creation of these new reachable states helps to trigger and propagate the Trojan effect more easily. Experimental results on ISCAS´89 benchmarks show that this method can effectively uncover Trojans which are otherwise very difficult to detect in the normal functional mode. In addition, partitioning the flip-flops of the circuit into different groups and selecting the output (Q or Q) based on input controlled ENABLE signals conceal its actual functionality beyond simple recognition thereby making it difficult for the adversary to implant Trojans.
Keywords :
design for testability; flip-flops; invasive software; reachability analysis; state-space methods; IC; ISCAS´89 benchmarks; ODETTE; Q signals; Trojan effect; Trojan implantations; embedded Trojan detection; flip-flops partitioning; normal functional mode; reachable states; state-space variation; two-step nonscan design-for-test methodology; Delay; Integrated circuits; Logic gates; Multiplexing; Pins; Trojan horses;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2011 IEEE International Symposium on
Conference_Location :
San Diego CA
Print_ISBN :
978-1-4577-1059-9
Type :
conf
DOI :
10.1109/HST.2011.5954989
Filename :
5954989
Link To Document :
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