DocumentCode :
23120
Title :
High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain: V_{\\rm th} Tuning, Variability, Access Resistance, and Mobility Issues
Author :
Villalon, A. ; Le Royer, Cyrille ; Cristoloveanu, S. ; Casse, M. ; Cooper, Daniel ; Mazurier, J. ; Previtali, B. ; Tabone, C. ; Perreau, P. ; Hartmann, J.-M. ; Scheiblin, P. ; Allain, F. ; Andrieu, F. ; Weber, Olivier ; Faynot, O.
Author_Institution :
French Atomic Energy and Alternative Energies Commission, Laboratory for Electronics and Information Technology, Grenoble, France
Volume :
60
Issue :
5
fYear :
2013
fDate :
May-13
Firstpage :
1568
Lastpage :
1574
Abstract :
We report on ultrascaled (L_{G}=23~{\\rm nm}) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded {\\rm Si}_{0.7}{\\rm Ge}_{0.3}({:}B) raised source and drain (RSD) for V_{\\rm th,p} tuning and smart strain management. In-depth electrical characterizations point out the {+}{120}\\hbox {-}{\\rm mV}~V_{\\rm th,p} tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% R_{\\rm access} reduction with SiGe RSD and {+}{\\rm 330%} mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference.
Keywords :
High K dielectric materials; MOSFET circuits; Resistance; Silicon germanium; ${rm V}_{rm th}$ variability; Access resistance; FDSOI; SiGe; dual-channel; mobility; pMOSFET; strain;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2013.2255055
Filename :
6502683
Link To Document :
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