Design issues in radix-4 SRT square root & divide unit

This paper introduces a number of design issues not covered in the open literature that arose during the design of a radix-4 SRT divide/square root unit for a vector processing chip. These include compression of the partial remainder´s m.s.b.´s, accelerated quotient/root digit selection, and simple formation of constants for updating square root residues. An important constraint on the design was to achieve target performance without infringing a number of existing patents.