Design issues in radix-4 SRT square root & divide unit

Author

Burgess, Neil ; Hinds, Chris

Author_Institution

Cardiff Sch. of Eng., Cardiff Univ., UK

Volume

2

fYear

2001

fDate

4-7 Nov. 2001

Firstpage

1646

Abstract

This paper introduces a number of design issues not covered in the open literature that arose during the design of a radix-4 SRT divide/square root unit for a vector processing chip. These include compression of the partial remainder´s m.s.b.´s, accelerated quotient/root digit selection, and simple formation of constants for updating square root residues. An important constraint on the design was to achieve target performance without infringing a number of existing patents.

Keywords

VLSI; dividing circuits; floating point arithmetic; integrated circuit design; vector processor systems; IEEE floating-point standard; VLSI implementation; accelerated quotient/root digit selection; constants formation; design issues; partial remainder MSB compression; patents; radix-4 SRT divide/square root unit; square root residues updating; vector processing chip; Acceleration; Adders; Circuits; Delay; Design engineering; Difference equations; Logic; Multiplexing; Road transportation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7147-X

Type

conf

DOI

10.1109/ACSSC.2001.987764

Filename

987764