Efficient integer multiplication overflow detection circuits

Multiplication of two n-bit integers produces a 2n-bit product. To allow the result to be stored in the same format as the inputs, many processors return the n least significant bits of the product and an overflow flag. This paper describes methods for integer multiplication with overflow detection for unsigned and two´s complement numbers. A method for combining unsigned and two´s complement integer multiplication with overflow detection is also presented. The overflow detection circuits presented in this paper have O(n) gates and O(log(n)) delay, which makes them more efficient than previous overflow detection circuits.