Application of logical effort techniques for speed optimization and analysis of representative adders

Author

Dao, Hoang ; Oklobdzija, V.G.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA

Volume

2

fYear

2001

fDate

4-7 Nov. 2001

Firstpage

1666

Abstract

This paper presents the transistor-level analysis of contemporary 64-bit adders. The logical effort technique is applied to provide more descriptive presentation of the delay and circuit architecture. It also enables optimization of gate size for optimal performance. The selected adders are dynamic carry-lookahead adder (DCLA), static carry-select adder (SCSA), dynamic Kogge-Stone adder (DKSA) and Ling/conditional-sum adder (DLCNSA). The results match well with simulation using 0.18 /spl mu/m, 1.8 V CMOS. Adders with fewer levels in the critical path show superior performance. In particular, for dynamic adders, a 0.6-FO4 per-gate delay improvement was observed.

Keywords

CMOS logic circuits; adders; carry logic; circuit optimisation; delays; 0.18 micron; 1.8 V; 64 bit; 64-bit adders; CMOS; DCLA; DKSA; DLCNSA; Ling/conditional-sum adder; SCSA; circuit architecture; critical path; delay; dynamic Kogge-Stone adder; dynamic adders; dynamic carry-lookahead adder; gate size; logical effort techniques; representative adders; speed optimization; static carry-select adder; transistor-level analysis; Added delay; Adders; Application software; Capacitance; Circuit simulation; Computer architecture; Delay effects; Delay estimation; Inverters; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-7803-7147-X

Type

conf

DOI

10.1109/ACSSC.2001.987768

Filename

987768