Title :
A sigma-delta based square-law compandor
Author :
Takasuka, Kaoru ; Hisajima, Hiroshi ; Takahashi, Kennichi ; Barlow, Allen
Author_Institution :
Asahi Kasei Microsyst., Tokyo, Japan
Abstract :
A compandor (compressor and expander) architecture for telecom applications is discussed. It reduces the number of off-chip components and allows full transceiver signal paths to be integrated and operated from a single supply as low as 3 V. Measured dynamic range is greater than 60 dB, with noise and distortion less than 57 dB. Both the 3 V and 5 V versions were implemented in a 2 μm, double-poly, double metal CMOS process. The compressor and expander occupy the same die area: 2.5 mm2 each. The only off-chip components are value insensitive: two DC blocking capacitors
Keywords :
CMOS integrated circuits; compandors; integrated circuit technology; 2 micron; 3 V; 5 V; DC blocking capacitors; compressor; double metal CMOS process; double-poly; dynamic range; expander; off-chip components; sigma-delta based square-law compandor; single supply; telecom applications; transceiver signal paths; Assembly; Circuits; Clocks; Delta-sigma modulation; Distortion measurement; Dynamic range; Noise measurement; Rectifiers; Telecommunications; Transceivers;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124722
