Title :
A new study of the junction leakage current due to 45/spl deg/-off active pattern after LOCOS process
Author :
Itoh, M. ; Habutsu, Y. ; Kuroda, S. ; Nagatomo, Y. ; Ino, M.
Author_Institution :
VLSI R&D Center, Oki Electr. Ind. Co. Ltd., Tokyo, Japan
Abstract :
Influence of LOCOS process induced stress on junction leakage current is studied. The junction leakage current increases with increasing field oxide and Si/sub 3/N/sub 4/ film thickness. Furthermore the junction leakage current depends on active pattern direction. From evaluation of resolve shear stress for glide direction, the junction leakage current at the active edge inclined 45/spl deg/ to orientation flat is affected by shear stress more than that at active edge perpendicular to the flat. Origin of the junction leakage current is generation center produced by the shear stress.<>
Keywords :
DRAM chips; MOS integrated circuits; characteristics measurement; integrated circuit technology; oxidation; DRAMs; LOCOS process; MOS integrated circuits; Si/sub 3/N/sub 4/; active pattern; field oxide; generation center; glide direction; junction leakage current; oxide isolation; resolve shear stress; Capacitors; Energy consumption; Etching; Leakage current; Low voltage; Random access memory; Research and development; Silicon; Stress; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347206