Latch-up performance of a sub-0.5 micron inter-well deep trench technology

The latch-up performance of a 3.3 volt, sub-0.5 micron, non-epitaxial bulk CMOS technology is described. For the first time, we present measured data which shows the holding voltage of the inter-well deep trench structure increases with reduced N/sup +P/sup +/ spacing. All other technologies, including the thin epi on P/sup +/ substrate process, suffer a decrease in holding voltage as the N/sup +P/sup +/ spacing is reduced. PISCES 2D simulations illustrate that the increase in holding voltage for the inter-well deep trench structure is due to enhanced current confinement along the trench sidewall. For the PNPN test device with an N/sup +P/sup +/ spacing of 2 /spl mu/m, the holding voltage is as high as 4.8 volts for the inter-well deep trench structure as compared to 1.5 volts for the bulk CMOS structure. The inter-well deep trench technology provides a 10/spl times/ improvement in holding current (60 mA) as compared to non-trench, bulk CMOS (6 mA). The fabricated inter-well deep trench structure also demonstrates excellent immunity to sidewall inversion, with sidewall leakage current less than 0.08 pAspl mu/m.<>