Exploring the optimum buffer size of an emerging stream cipher engine

One of crucial points for ubiquitous network is to keep the temporary security without relying on permanent network infrastructure. Considering a practical solution of ubiquitous security is a safety aware, high-performed single chip processor, we have exploited a multimedia stream cipher engine and its VLSI chip implementation. In order to keep security, usability, speed, and power consciousness, the stream cipher engine takes a compact multicore architecture. Each core implements a double cipher scheme that covers RAC (random addressing cryptography) and data sealing. The double cipher is microarchitecture-based, software-transparent hardware cryptography that offers the protection of the whole data with negligible hardware cost and moderate performance overhead. We studied in previous works the chip implementation of the stream cipher engine by using 0.18-mum standard cell CMOS technologies. Prospective specifications of chips were also examined by means of rough evaluation. This paper focuses on the latest version of the stream cipher engine chip and evaluates more in detail power dissipation, clock speed, running time, and throughput by using Synopsys Design Compiler. From the cipher streaming buffer size dependency of these specificative factors, we make clear the tradeoff between them and achieve the guideline of optimum buffer size in view of safety and performance for ubiquitous computing.