Title :
A programmable 32 tap digital interpolation filter in 1.5 μm CMOS with 80 MHz output data rate
Author :
Haberecht, Wolfgang ; DeMan, Erik ; Schulz, Michael
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
A 32 tap programmable, digital FIR filter for pulse shaping is presented. The filter performs interpolation of the input data sampled at a maximum clock frequency of 40 MHz. The output data rate is 80 MHz. The data inputs and outputs are emitter-coupled-logic (ECL)-compatible. The stepped coefficient set contains 256 coefficient bits, which can be serially loaded. To reduce the effect of power bus switching noise (due to the large clock system capacitance) a special clock system with distributed clock subsystems is used. With a sequence of 3500 deterministic test vectors a 98% stuck-at fault coverage can be achieved. The chip contains 159.022 transistors on a total area of 78 mm 2 and has been realized in 1.5 μm CMOS technology
Keywords :
CMOS integrated circuits; VLSI; digital filters; pulse shaping circuits; 1.5 micron; 40 MHz; 80 MHz; 80 MHz output data rate; CMOS technology; ECL compatible; clock system; digital FIR filter; digital interpolation filter; distributed clock subsystems; maximum clock frequency; programmable filters; pulse shaping; stepped coefficient set; stuck-at fault coverage; CMOS technology; Capacitance; Clocks; Digital filters; Finite impulse response filter; Frequency; Interpolation; Noise reduction; Pulse shaping methods; Testing;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124724
