Title :
NAND-structured cell technologies for low cost 256 Mb DRAMs
Author :
Hamamoto, T. ; Yamada, T. ; Aoki, M. ; Ishibashi, S. ; Kawaguchiya, H. ; Ishibashi, Y. ; Hashimoto, K. ; Kanai, H.
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
NAND-structured cell technologies for low cost DRAMs have been demonstrated. Two kinds of cell structure have been developed, a stacked type NAND-structured cell for 256 Mb and a trench type cell for 256 Mb and beyond. In order to maximize plane view area of the storage node of the NAND-structured STC, a transparent phase shift mask has been used. Sufficient storage capacitance can be obtained with one lithography and one RIE process. The NAND-structured trench cell has advantage for miniaturization. In this cell configuration, the deep trench for the capacitor also used for the trench isolation between neighboring cells. The junction leakage current from the storage node can be reduced by using a p/sup +/ substrate.<>
Keywords :
CMOS integrated circuits; DRAM chips; integrated circuit technology; photolithography; sputter etching; 256 Mbit; NAND-structured cell technologies; RIE process; dynamic RAM; junction leakage current; lithography; low cost 256 Mb DRAMs; p/sup +/ substrate; stacked typecell; storage capacitance; transparent phase shift mask; trench isolation; trench type cell; Capacitance; Capacitors; Costs; Fabrication; Lithography; Phase shifters; Plugs; Random access memory; Substrates; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347229
