DocumentCode :
2312611
Title :
Design of power-optimal buffers tunable to process variability
Author :
Lok, Mario ; He, Ku ; Mani, Murari ; Caramanis, Constantine ; Orshansky, Michael
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX, USA
fYear :
2010
fDate :
17-18 Oct. 2010
Firstpage :
1
Lastpage :
4
Abstract :
In many digital designs, multi-stage tapered buffers are needed to drive large capacitive loads. These buffers contribute a significant percentage of overall power. In this paper, we propose two novel tunable buffer designs that enable power reduction in the presence of process variation. A strategy to derive the optimal buffer size and tuning rule in post-silicon phase is developed. By comparing several tunable buffer circuit topologies, we also demonstrate the tradeoffs in tunable buffer topology selection as a function of switching activity, timing requirements, and the magnitude of process variation. Using a combination of HSPICE simulations and our optimization algorithm, we show that up to 30% average power reduction can be achieved with the proposed buffer structures.
Keywords :
SPICE; buffer circuits; logic design; optimisation; HSPICE simulation; capacitive load; digital design; multistage tapered buffer; optimization algorithm; post-silicon phase; power reduction; power-optimal buffer; tunable buffer circuit topology; tunable buffer design; tuning rule; Decision support systems; Helium; Adaptive Design; Buffer Design; Low Power Design; Post-Silicon Tuning; Statistical Design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems Workshop (DCAS), 2010 IEEE Dallas
Conference_Location :
Richardson, TX
Print_ISBN :
978-1-4244-9535-1
Electronic_ISBN :
978-1-4244-9534-4
Type :
conf
DOI :
10.1109/DCAS.2010.5955033
Filename :
5955033
Link To Document :
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