Implementation of Spatial Domain Filters for Cell Broadband Engine

The cell broadband engine architecture (CBEA) is a nine-core architecture, including a 64-bit powerPC processor element (PPE) and eight synergistic processor elements (SPE) which offers a raw compute power of up to 200 GFlops per 3.2 GHz chip. The cell bears a huge potential for compute intensive applications but also requires addressing the challenges caused by this processorpsilas unconventional architecture. In this paper we describe an implementation of spatial domain filtering which have been re-architected for implementation on the cell broadband engine. The results are compared with the performance of the algorithm on conventional platforms. In addition we show our measurements and speed-up.