Title :
A 40 MHz programmable and reconfigurable filter processor
Author :
Cai, Mike ; Luthi, Daniel ; Ruetz, Peter ; Ang, Peng
Author_Institution :
LSI Logic Corp., Menlo Park, CA, USA
Abstract :
A programmable and reconfigurable filter processor comprising four 16×16 multiplier-accumulators is presented. The processor, fabricated in a 1.5-μm 2-layer metal CMOS process, has been tested and is fully functional up to 40 MHz clock frequency. It can be programmed and reconfigured via an on-chip sequencer for a range of applications, including radar signal processing, image processing, discrete cosine transform, discrete Fourier transform, and other general inner product applications
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; two-dimensional digital filters; 1.5 micron; 16 bit; 2-layer metal CMOS process; 40 MHz; clock frequency; discrete Fourier transform; discrete cosine transform; general inner product applications; image processing; multiplier-accumulators; on-chip sequencer; programmable filter processor; radar signal processing; reconfigurable filter processor; Adaptive filters; Adders; Clocks; Delay; Digital signal processing; Discrete cosine transforms; Image processing; Radar applications; Radar signal processing; Registers;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124725
