Scaling limitations of gate oxide in p/sup +/ polysilicon gate MOS structures for sub-quarter micron CMOS devices

Author

Uwasawa, K. ; Mogami, T. ; Kunio, T. ; Fukuma, M.

Author_Institution

Microelectronics Res. Labs., NEC Corp., Kangawa, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

895

Lastpage

898

Abstract

The reliability of pure gate oxide in BF/sub 2sup +/- or B/sup +/-implanted p/sup +/ polysilicon gate MOS structures was investigated. It was found that gate oxide degradation with p/sup */-gate is explained by enhanced charge trapping, due to boron penetration, in thin strained layer formed during initial oxidation. A scaling scenario on the gate oxide reliability for p/sup +/-gate PMOSFETs is discussed. It was demonstrated that reliable 4 nm-thick pure gate oxide for O.1 /spl mu/m PMOSFETs can be realized by optimizing fabrication conditions.<>

Keywords

insulated gate field effect transistors; ion implantation; oxidation; reliability; 0.1 micron; B/sup +/-implantation; BF/sub 2sup +/-implantation; Si:B-SiO/sub 2/; Si:BF/sub 2/-SiO/sub 2/; charge trapping; fabrication; gate oxide degradation; gate oxide reliability; oxidation; p/sup +/ polysilicon gate MOS structures; p/sup +/-gate PMOSFETs; reliability; scaling; strained layer; sub-quarter micron CMOS devices; Annealing; Boron; Breakdown voltage; Degradation; Dielectric breakdown; Dielectric measurements; Electric breakdown; Fabrication; MOS capacitors; MOSFETs;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347256

Filename

347256