Scaling limitations of gate oxide in p/sup +/ polysilicon gate MOS structures for sub-quarter micron CMOS devices

The reliability of pure gate oxide in BF/sub 2sup +/- or B/sup +/-implanted p/sup +/ polysilicon gate MOS structures was investigated. It was found that gate oxide degradation with p/sup */-gate is explained by enhanced charge trapping, due to boron penetration, in thin strained layer formed during initial oxidation. A scaling scenario on the gate oxide reliability for p/sup +/-gate PMOSFETs is discussed. It was demonstrated that reliable 4 nm-thick pure gate oxide for O.1 /spl mu/m PMOSFETs can be realized by optimizing fabrication conditions.<>