Submicron CMOS gate electrode discontinuity: electrical signature and effect on circuit speed

Author

Jenkins, K.A. ; Burghartz, J.N. ; Agnello, P.D. ; Heidel, D.F. ; Wong, C.Y.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

891

Lastpage

894

Abstract

The importance of vertical continuity of the gate electrodes of submicron CMOS circuits is discussed. A high frequency technique for assessing this continuity is demonstrated. An example of a gate structure with poor vertical continuity is shown, and the effect on circuit operation is presented.<>

Keywords

CMOS integrated circuits; electric resistance measurement; insulated gate field effect transistors; integrated circuit testing; CMOS gate electrode discontinuity; HF method; circuit speed effect; electrical signature; high frequency technique; submicron CMOS circuits; vertical continuity; CMOS technology; Conductors; Contact resistance; Electrical resistance measurement; Electrodes; Integrated circuit interconnections; Ring oscillators; Silicides; Tin; Titanium;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347257

Filename

347257

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2312975