Ultranarrow trench-isolated 0.2-/spl mu/m CMOS and its application to ultralow-power frequency dividers

Author

Inokawa, H. ; Yamamoto, Y. ; Okazaki, Y. ; Kobayashi, T. ; Miyake, M. ; Ishii, H.

Author_Institution

NTT LSI Labs., Atsugi, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

887

Lastpage

890

Abstract

We applied shadow trench isolation to 0.2-/spl mu/m gate-length CMOS to fully utilize its low-power capability. With a proper design of device structure and dopant concentrations, the narrow-channel effect was not conspicuous down to the effective channel width of 0.1 /spl mu/m, and inter-device isolation was secured down to the coded isolation width of 0.28 /spl mu/m. Using the narrow-channel devices, a frequency divider circuit operating with a first-stage power dissipation of 12 fJ per clock has been fabricated.<>

Keywords

CMOS integrated circuits; frequency dividers; integrated circuit technology; integrated logic circuits; 0.1 to 0.28 micron; dopant concentration; inter-device isolation; low-power capability; narrow-channel devices; shadow trench isolation; submicron process; ultralow-power frequency dividers; ultranarrow trench-isolated CMOS; Circuits; Clocks; Delay effects; Electrons; Fabrication; Frequency conversion; Leakage current; MOSFETs; Power dissipation; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347258

Filename

347258