SOI for a 1-volt CMOS technology and application to a 512 Kb SRAM with 3.5 ns access time

Author

Shahidi, G.G. ; Ning, T.H. ; Chappell, T.I. ; Comfort, J.H. ; Chappell, B.A. ; Franch, R. ; Anderson, C.J. ; Cook, P.W. ; Schuster, S.E. ; Rosenfield, M.G. ; Polcari, M.R. ; Dennard, R.H. ; Davari, B.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

813

Lastpage

816

Abstract

In this paper a CMOS technology that is optimum for low voltage (in the I-volt range) applications is presented. Thin but undepleted SOI is used as the substrate, which gives low junction capacitance and no body effect. Furthermore floating body effects causes a reduction of subthreshold slope at high drain bias. This lowers the high-V/sub DS/ threshold to be used, which increases the current drive without significant increase in the off-current. This technology was applied to a high performance 512 Kb SRAM. Access time of 3.5 ns at 1 V was obtained.<>

Keywords

CMOS integrated circuits; SRAM chips; integrated circuit technology; semiconductor-insulator boundaries; silicon; 1 V; 3.5 ns; 512 Kbit; CMOS technology; SOI; SRAM; access time; current drive; drain bias; floating body effects; junction capacitance; subthreshold slope; CMOS technology; Capacitance; Circuits; Clocks; Delay; Frequency; Low voltage; Power supplies; Random access memory; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347275

Filename

347275