An excellent weight-updating-linearity synapse memory cell for self-learning neuron MOS neural networks

A new synapse cell circuit employing a floating-gate memory has been developed which is characterized by an excellent weight-updating linearity. Such a feature has been realized for the first time by employing a simple self-feedback regime in each cell circuitry. The new cell is composed of only seven transistors and inherits all the advanced features of the old six-transistor cell, such as the standby-power free and dual polarity characteristics, thus making it fully compatible to the hardware learning architecture of the neuron MOS neural network. The basic characteristics of the cell are demonstrated using test circuits fabricated by a double-polysilicon CMOS process.<>