DocumentCode :
2313344
Title :
Design and VLSI implementation of a Low Probability of Error Viterbi Decoder
Author :
Arun, C. ; Rajamani, V.
Author_Institution :
Dept. of Inf. Technol., Venkateswara Coll. of Eng., Chennai
fYear :
2008
fDate :
16-18 July 2008
Firstpage :
418
Lastpage :
423
Abstract :
The use of error-correcting codes has proven to be an effective way to overcome data corruption in digital wireless communication channels, enabling reliable transmission to be achieved over noisy and fading channels. In this paper a novel approach to design a high throughput with reduced bit error probability Viterbi decoder is described and implemented. Low bit error rate (BER) can be achieved by increasing the free distance (dfree) of the Viterbi decoder without increasing complexity. The increase in dfree has been achieved by a proposed non-polynomial convolutional code method. A decoder system with code rate of k/n=frac14, constrain length K=3 has been implemented on Xilinx Spartan-III. The performance of viterbi decoder with the proposed method has been improved from 27% to 75% of errors are detected and corrected. We have also achieved a high speed (84.958 Mbps) and low Bit Error Rate (BER) viterbi decoder. Experimental results shows that the proposed viterbi decoder provides satisfactory Pe performance and high operating speed under various conditions including AWGN, co-channel interference and adjacent channel interference environments.
Keywords :
VLSI; Viterbi decoding; channel coding; convolutional codes; error correction codes; error statistics; fading channels; VLSI implementation; bit error probability Viterbi decoder; digital wireless communication channels; error-correcting codes; fading channels; free distance; noisy channels; nonpolynomial convolutional code method; reliable transmission; AWGN; Additive white noise; Bit error rate; Decoding; Error correction codes; Gaussian noise; Interchannel interference; Very large scale integration; Viterbi algorithm; Wireless communication; Add Compare Select (ACS); Branch Metric Unit (BMU); Low Bit Error Rate; Trace Back Unit (TBU); Viterbi algorithm; free distance; non-polynomial approach;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging Trends in Engineering and Technology, 2008. ICETET '08. First International Conference on
Conference_Location :
Nagpur, Maharashtra
Print_ISBN :
978-0-7695-3267-7
Electronic_ISBN :
978-0-7695-3267-7
Type :
conf
DOI :
10.1109/ICETET.2008.180
Filename :
4579936
Link To Document :
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