Projecting CMOS circuit hot-carrier reliability from DC device lifetime

Author

Quader, K.N. ; Ko, P.K. ; Chenming Hu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

511

Lastpage

514

Abstract

We present generalized hot-carrier-reliability technology qualification and circuit design rules. The inverse duty factors, i.e. DC to AC time conversion factors for N- and P-MOSFETS are found to be 4/ft/sub rise/, and 10/ft/sub fall/ or 120 and 300 respectively. Typically, /spl Deltaspl tau/spl tau/ of an inverter is 1/4 /spl Delta/I/sub dI/sub d/ of NMOSFET minus 1/2 /spl Delta/I/sub dI/sub d/ of PMOSFET. The proposed design rules are valid for both 5 V and 3.3 V technologies and can be easily incorporated into existing DC lifetime prediction routines.<>

Keywords

CMOS integrated circuits; circuit reliability; hot carriers; insulated gate field effect transistors; integrated circuit technology; integrated logic circuits; 3.3 V; 5 V; CMOS circuit; DC device lifetime; DC/AC time conversion factors; NMOSFET; PMOSFET; circuit design rules; hot-carrier reliability; inverse duty factors; lifetime prediction routines; technology qualification; CMOS technology; Degradation; Frequency; Hot carriers; Inverters; MOSFET circuits; Neodymium; Qualifications; Ring oscillators; Stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347299

Filename

347299