Title :
A physical poly-silicon thin film transistor model for circuit simulations
Author :
Li, C.C. ; Ikeda, K. ; Inoue, T. ; Ko, P.K.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
This paper presents a poly-silicon thin film transistor model for circuit simulations. The drain current model includes the effects of hot carriers, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is weakly linked to the drain current and its derivatives. This model has been implemented in a SPICE simulation and experimental results are compared.<>
Keywords :
SPICE; circuit analysis computing; field effect transistor circuits; hot carriers; semiconductor device models; thin film transistors; SPICE; Si; capacitance; channel length modulation; circuit simulations; drain current; drain induced barrier lowering; gate induced drain leakage; hot carriers; poly-silicon thin film transistor model; Circuit simulation; Convergence; Hot carrier effects; SPICE; Smoothing methods; Temperature; Thin film transistors; Voltage;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347302
