A novel method to determine gate-drain overlap in sub-micron transistors

This paper describes a novel method to determine the gate-drain overlap in a sub-micron channel length transistor under circuit operating conditions. The method essentially entails applying 500 ns wide square wave pulses to the MOSFET drain and measuring the drain current response as determined by the gate coupling which, in turn, is determined by the gate-drain overlap capacitance. After obtaining an accurate DC current model, the pulse measurements are matched with SPICE simulations to determine the accurate value for total lateral diffusion.<>