Timing optimizations in a high-level synthesis system

Two alternative techniques for meeting tight timing constraints on a network, fanout compensation and resource rearchitecting, are discussed, and it is shown how these can be used together to obviate the need for expensive logic optimization steps in some cases. Both these techniques have been successfully used in SilcSyn, an ASIC design synthesis system from Silc Technologies. All techniques presented are targeted towards systems that synthesize designs in standard cell or gate array libraries