High-performance CMOS with oxidation-planarized twin tubs and one-mask sealed diffusion-junctions

Author

Liu, C.T. ; Luftman, H. ; Lin, W. ; Chang, C.P. ; Yang, T.S. ; Fu, C.C. ; Lee, K.H. ; Liu, R. ; Yaney, D.S.

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

437

Lastpage

440

Abstract

Issues of submicron integration in vertical topography, junction silicide, and contact integrity are summarized. Examples include (1) high cost of twin-tub formation to achieve planarity at tub boundaries, (2) silicide-related nonuniformity or defects on shallow junctions, and (3) coverage of a TiN diffusion barrier layer at bottom corners of contact windows. We present a simple process to attack the issues. The process requires only ten masks for a full-CMOS integration with two-level metallization. It also improves the integration density and circuit performance.<>

Keywords

CMOS integrated circuits; integrated circuit technology; masks; metallisation; oxidation; CMOS; TiN diffusion barrier layer; circuit performance; contact integrity; contact windows; integration density; junction silicide; one-mask sealed diffusion-junctions; oxidation-planarized twin tubs; submicron integration; two-level metallization; vertical topography; Capacitance; Circuit optimization; Costs; Electric resistance; Implants; Oxidation; Silicides; Silicon; Stress; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347316

Filename

347316