Topology decomposition for area-minimum multi-stage complex gates synthesis

A synthesis method for area-minimum multi-stage complex gates is proposed. It is based on a novel transistor-level multistage decomposition and transistor sizing method. A large single-stage complex gate is topologically decomposed into multistage circuits recursively. After the topology decompositions, transistor sizes of decomposed circuits are optimized using a two-step sizing method in order, to evaluate the real area-minimum circuit topology for given delay time and load capacitance. Experimental results are given to demonstrate that the proposed method can successfully generate the most area-efficient topology while simultaneously optimizing the sizes of transistors