Implementation of RS encoder for CCSDS

Error correction coding technology is a valid way to improve the reliability of communication system in which information will be distorted duo to various noises in the channel. This paper considers RS code as the error correction code, and gives the implementation of the RS encoder under CCSDS standard. The implementation of the parallel multiplier with constant coefficients under the natural base is proposed on the basis of the coding theory of the RS code and the design of the basic unit circuit. In addition, the RS encoder is modeled by MATLAB which prepares procedure´s debug for the implementation of the RS encoder. Furthermore, the RS encoder is designed on FPGA by using VHDL, and is simulated under the environment of Modelsim SE 6.5d. The performance of the RS encoder is verified by comparison with the theoretical results. The FPGA implementation shows that the design of the RS encoder occupies minimal hardware resources and can apply to high-speed occasions.