Title :
Analysis and design of CMOS Manchester adders with variable carry-skip
Author :
Chan, Pak K. ; Schlag, Martine D F
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
A popular VLSI adder implementation is the Manchester adder using dynamic (precharge) logic, where the ripple-carry propagation delay of a block is proportional to the square of its size. The authors examine two different CMOS implementations of the Manchester adder, analyzing them with the RC timing model, which provides a unified way of analyzing both CMOS circuits and interconnect. Based on the RC timing model, they develop efficient (polynomial) algorithms to determine near-optimal, as well as optimal, block sizes for the one-level Manchester adder with variable carry-skip
Keywords :
CMOS integrated circuits; VLSI; adders; digital arithmetic; CMOS Manchester adders; RC timing model; VLSI; interconnect; ripple-carry propagation delay; variable carry-skip; Adders; CMOS logic circuits; Circuit analysis; Integrated circuit interconnections; Polynomials; Propagation delay; Semiconductor device modeling; Signal design; Timing; Very large scale integration;
Conference_Titel :
Computer Arithmetic, 1989., Proceedings of 9th Symposium on
Conference_Location :
Santa Monica, CA
Print_ISBN :
0-8186-8963-3
DOI :
10.1109/ARITH.1989.72813
