Implementation of SMS4 Block Cipher on FPGA

Author

Jin, Yier ; Shen, Haibin ; You, Rongquan

Author_Institution

Inst. of VLSI Design, Zhejiang Univ., Hangzhou

fYear

2006

fDate

25-27 Oct. 2006

Firstpage

1

Lastpage

4

Abstract

This paper describes two encryption designs of Chinese wireless local area network block cipher standard - SMS4 algorithm. Then these two designs are implemented on Xilinx Virtex-4 FPGA devices. The first (pipelined) design is optimized in order to reduce time delay and the encryption core has a throughput of 24 Gb/s. The second (folded) design is optimized in order to minimize area coverage and the encryption core only needs 380 CLB slices with throughput of 740 Mb/s. There are no known hardware implementations of an encryption SMS4 designs.

Keywords

cryptography; field programmable gate arrays; wireless LAN; 24 Gbit/s; 740 Mbit/s; Chinese wireless local area network block cipher standard; SMS4 block cipher; Xilinx Virtex-4 FPGA devices; encryption designs; Algorithm design and analysis; Computer architecture; Cryptography; Design optimization; Field programmable gate arrays; Iterative algorithms; Random access memory; Throughput; Very large scale integration; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Networking in China, 2006. ChinaCom '06. First International Conference on

Conference_Location

Beijing

Print_ISBN

1-4244-0463-0

Electronic_ISBN

1-4244-0463-0

Type

conf

DOI

10.1109/CHINACOM.2006.344900

Filename

4149865