DocumentCode :
2314717
Title :
Design of Optimal Architectures Using Homogeneous Routers for Application Specific Network on Chip
Author :
Yalamanchili, Kishore ; Pasalapudi, Aditya ; Majeti, Deepak ; Sunitha, V.
Author_Institution :
Dhirubhai Ambani Inst. of Inf. & Commun. Technol., Gandhinagar
fYear :
2008
fDate :
16-18 July 2008
Firstpage :
873
Lastpage :
877
Abstract :
Network on chip (NoC) is evolving as a promising paradigm for high density SoC (System on Chip) designs. It is introduced as a remedy for the challenges introduced by the current interconnects in VLSI chips. NoC design involves decisions at various levels of hierarchy. Architecture selection is one of the most important aspects of NoC design in general and application specific NoC in particular. The paper aims in presenting algorithm for generating optimal topologies with homogeneous routers from a given communication task graph.
Keywords :
VLSI; integrated circuit design; integrated circuit interconnections; network-on-chip; NoC; VLSI chips; high density SoC; homogeneous routers; optimal topologies; specific network on chip; task graph; Bandwidth; Clocks; Communications technology; Delay; Design engineering; Energy consumption; Network topology; Network-on-a-chip; System-on-a-chip; Very large scale integration; Greedy Algorithm; Homogeneous Routers; Low Energy; Network on Chip; Optimal Tree Topologies;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging Trends in Engineering and Technology, 2008. ICETET '08. First International Conference on
Conference_Location :
Nagpur, Maharashtra
Print_ISBN :
978-0-7695-3267-7
Electronic_ISBN :
978-0-7695-3267-7
Type :
conf
DOI :
10.1109/ICETET.2008.36
Filename :
4580025
Link To Document :
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