An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage

Author

Moazzeni, Shadi ; Poormozaffari, Saadat ; Emami, Amin

Author_Institution

Comput. & IT Dept., Amirkabir Univ. of Technol., Tehran, Iran

fYear

2009

fDate

7-9 Dec. 2009

Firstpage

55

Lastpage

60

Abstract

A technique is described for the automatic insertion of fault models into VHDL gate models, using a specific algorithm to calculate fault coverage. This procedure does not require any modification to the structural description of a circuit using these models. Additional optimized algorithms are added to illustrate better calculation of fault coverage of a VHDL based combinational logic circuit.

Keywords

combinational circuits; fault simulation; hardware description languages; logic simulation; VHDL gate models; automatic insertion; combinational logic circuit; fault coverage; fault models; optimized simulation-based fault injection; test vector generation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Electronic equipment testing; Fault detection; Hardware; System testing; Fault Coverage; Fault Equivalence; Fault injection; Stuck-at-fault; Test vector generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification (MTV), 2009 10th International Workshop on

Conference_Location

Austin, TX

ISSN

1550-4093

Print_ISBN

978-1-4244-6479-1

Electronic_ISBN

1550-4093

Type

conf

DOI

10.1109/MTV.2009.22

Filename

5460810