A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Transition Tests

Author

Zeng, Jing ; Wang, Jing ; Mateja, Michael

Author_Institution

Adv. Micro Devices, Austin, TX, USA

fYear

2009

fDate

7-9 Dec. 2009

Firstpage

49

Lastpage

54

Abstract

Speed path identification is an indispensable step for pushing the design timing wall. We propose a new at-speed diagnosis methodology. Key characteristics of the methodology are (a) path-oriented diagnosis, (b) failing frequency guided, and (d) identified speed paths referenced in the timing verification design database. We demonstrate the effectiveness of our technique on a quad-core AMD OpteronÂ¿ Processor.

Keywords

fault diagnosis; logic design; logic testing; microprocessor chips; timing; at-speed diagnosis methodology; at-speed transition test; design timing wall; failing frequency guided; identified speed path; path-oriented timing-aware diagnosis; quad-core AMD Opteron processor; speed path identification; timing verification design database; Automatic test pattern generation; Circuits; Cost function; Fault diagnosis; Predictive models; Semiconductor device measurement; Silicon; Testing; Timing; Velocity measurement; at-speed logic diagnosis; general speed path profiling; path-oriented approach;

fLanguage

English

Publisher

ieee

Conference_Titel

Microprocessor Test and Verification (MTV), 2009 10th International Workshop on

Conference_Location

Austin, TX

ISSN

1550-4093

Print_ISBN

978-1-4244-6479-1

Electronic_ISBN

1550-4093

Type

conf

DOI

10.1109/MTV.2009.21

Filename

5460813