Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

Author

Lee, K.F. ; Yan, R.H. ; Jeon, D.Y. ; Chin, G.M. ; Kim, Y.O. ; Tennant, D.M. ; Razavi, B. ; Lin, H.D. ; Wey, Y.G. ; Westerwick, E.H. ; Morris, M.D. ; Johnson, R.W. ; Liu, T.M. ; Tarsia, M. ; Cerullo, M. ; Swartz, R.G. ; Ourmazd, A.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

131

Lastpage

134

Abstract

We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics.<>

Keywords

CMOS integrated circuits; integrated circuit technology; integrated logic circuits; ion implantation; 0.1 micron; 11.8 ps; 2.5 V; 8.5 GHz; CMOS technology; NMOS devices; PMOS devices; Si; bulk Si substrates; g-line lithography design rules; high speed CMOS performance; parasitics reduction; ring-oscillator gate delay; room temperature technology; vertical doping engineering; CMOS technology; Circuits; Delay; Doping; Frequency conversion; Frequency measurement; MOS devices; Parasitic capacitance; Ring oscillators; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347382

Filename

347382