Title :
Ultimate CMOS ULSI performance
Author_Institution :
IBM Corp., Essex Junction, VT, USA
Abstract :
Ultra-Large-Scale Integration (ULSI) CMOS technology is advancing beyond the realm of conventional scaling theory, requiring a new approach to the problem of scale reduction. Limits on active power are pushing the power supply voltage, V/sub DD/, downward, while increased MOSFET count is creating pressure to increase threshold-voltage, V/sub T/, to keep passive power (sub-threshold leakage) from growing. A conflict between the needs for lower V/sub DD/ and higher V/sub T/ thus arises. Power constraints alone, independent of other potential limitations, will lead to maximum performance at the 100-nm lithographic scale of approximately two to three times that of 0.5-/spl mu/m, 3.3 V CMOS technology.<>
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; 0.5 micron; 100 nm; 3.3 V; MOSFET count; ULSI CMOS technology; active power; lithographic scale; passive power; power supply voltage; scaling theory; sub-threshold leakage; threshold-voltage; ultimate performance; CMOS technology; MOSFET circuits; Microelectronics; Parasitic capacitance; Power MOSFET; Power dissipation; Power supplies; Silicon; Threshold voltage; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347386
