DocumentCode
2315129
Title
A highly manufacturable trench isolation process for deep submicron DRAMs
Author
Fazan, P.C. ; Mathews, V.K.
Author_Institution
Micron Technol. Inc., Boise, ID, USA
fYear
1993
fDate
5-8 Dec. 1993
Firstpage
57
Lastpage
60
Abstract
A simple Shallow Trench Isolation (STI) process is proposed for deep sub-micron DRAM applications. The features of this STI flow are tapered trench sidewalls, a slight trench reoxidation, a vertical B field implant, a CMP-only planarization, and disposable oxide spacers to smooth the trench corners. The scalability of this process makes it suitable for 256 Mb to 4 Gb DRAM generations.<>
Keywords
DRAM chips; integrated circuit technology; 256 Mbit to 4 Gbit; CMP-only planarization; Shallow Trench Isolation; deep submicron DRAMs; disposable oxide spacers; manufacture; scalability; tapered trench sidewalls; trench isolation; trench reoxidation; vertical B field implant; Chemical processes; Doping; Dry etching; Implants; Isolation technology; Manufacturing processes; Oxidation; Planarization; Random access memory; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-1450-6
Type
conf
DOI
10.1109/IEDM.1993.347399
Filename
347399
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