Title :
ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation
Author :
Eimori, T. ; Oashi, T. ; Kimura, H. ; Yamaguchi, Y. ; Iwamatsu, T. ; Tsuruda, T. ; Suma, M. ; Hidaka, H. ; Inoue, Y. ; Nishimura, T. ; Satoh, S. ; Miyoshi, H.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed.<>
Keywords :
CMOS integrated circuits; DRAM chips; SIMOX; VLSI; integrated circuit technology; metal-insulator-semiconductor devices; sputter etching; 0.5 micron; 2 V; CMOS/SIMOX technology; ECR etching; RAS access time; Si-SiO/sub 2/; ULSI DRAM; bit-line capacitance; fabrication; field-shield isolation; floating body effects; low-voltage operation; parasitic source/drain resistance; polysilicon pad; stacked capacitor cells; thin-film SOI devices; Capacitors; Etching; Insulator testing; Isolation technology; Oxygen; Random access memory; Semiconductor thin films; Silicon on insulator technology; Thin film devices; Ultra large scale integration;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347402
