Design of a 5mW capacitive accelerometer based on MEMS and CMOS technology

This work presents an open-loop, fully differential capacitive MEMS accelerometer implemented in CMOS technology. The mathematical model of this open-loop system is derived, which considers non-ideal factors in circuits such as nonlinear distortion and noises. These non-ideal factors have been discussed through system level simulation using MATLAB. Simulation results show that the system has good capacitive sensitivity and is robust to noises. The detailed design of interface circuit in the proposed MEMS accelerometer is presented, using sigma-delta (Σ-Δ) modulation. Finally, the chip-level physical layout of interface circuit is implemented and tested, using silicon-on-insulator (SOI) substrate with 1μm CMOS process. Results have shown the chip with area of 1.32mm² and power consumption of about 5mW. The proposed MEMS accelerometer is designed for acceleration of less than 5G, and its resolution is 1.923mG.