Real-time and extensible calculation of STAP weights on FPGA

Space-Time Adaptive Processing (STAP) technique can restrain the effects of interference and clutter effectively. However, the calculation of STAP weights, including QR decomposition (QRD) and solving linear equations needs intensive computation. This paper mainly focuses on improving the QRD algorithm and presents an efficient FPGA design, based on floating point IP core, which can meet the requirement of real-time and extensible computation of adaptive weights. In this work, the structure of QRD algorithm is adjusted for efficient implementation and the design is introduced in detail. The simulation by Modelsim software shows that the QRD time is 18.306us for 9 × 36 data matrix when the design works on 250MHZ and the platform is XC7Z020 FPGA.