A novel design of divider and structure for FPGA implementation in P code generator

The P-code generator is a critical component in P-code acquisition. The model of the generator is used to determine the register´s initial states. Consider the model is mainly consisted of six dividers, all of which have fixed width of dividend and divisor; two novel designs of divider based on the digit-recurrence division algorithm are presented that can improve the area-consuming and latency compared with the IP-based design. Moreover, a novel structure of the model is proposed and achieves more than half resources reduction compared with the original structure. The algorithms have been synthesized on a Xilinx Virtex-5 FPGA and implementation results are given.