A CMOS VLSI chess microprocessor

Author

Testa, James ; Despain, Alvin

Author_Institution

Div. of Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

The Berkeley Chess Microprocessor (BCM) is a 200000 transistor, 1.2 micron CMOS (N-Well) die, 11 mm by 9 mm in area. It can generate three million legal moves/s. The BCM´s novel architecture allows for evaluation of chess board positions several ply deep from the current board position. This chip has three evaluation innovations: (1) pins and X-ray attacks can be determined, (2) dynamic evaluation is possible, and (3) an ALU on each square can sum the values of attacking pieces. The evaluation innovations can be used to produce exponential search speedup for chess programs. This approach of mapping the problem´s topology into silicon is general enough to be used to produce exponential speedups in tree searches where interactions are considered in parallel

Keywords

CMOS integrated circuits; VLSI; computer games; microprocessor chips; multiprocessing systems; special purpose computers; 1.2 micron; 11 mm; ALU on each square; Berkeley Chess Microprocessor; CMOS; VLSI; X-ray attacks; chess programs; dynamic evaluation; evaluation innovations; evaluation of chess board positions; exponential search speedup; exponential speedups in tree searches; pin attack; Circuits; Computer architecture; Computer science; Data mining; Law; Legal factors; Microprocessors; Silicon; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124744

Filename

124744