FPGA-based Ultra-Low Latency HIL Fault Testing of a Permanent Magnet Motor Drive using RT-LAB-XSG

Real-time simulation of PMSM drives enables thorough testing of control strategies & software protection routines and therefore allows rapid deployment of vehicular or industrial applications. The proposed PMSM model is a phase domain model with sinusoidal flux induction. A 3-phase IGBT inverter drives the PMSM machine. Both models are implemented on an FPGA chip, without any VHDL coding, with the RT-LAB real-time simulation platform of Opal-RT Technologies using a Simulink blockset called Xilinx System Generator (XSG). The paper explains various aspects of the design of the motor drive models in fixed-point representation in XSG, as well as simulation validation against a standard PMSM drive model built in Simulink. The phase-domain PMSM drive model runs with an equivalent 10 nanosecond time step (100 MHz FPGA card) and has a latency of 300 nanoseconds (PMSM machine and inverter). The motor drive has a resulting total hardware-in-the-loop latency of 1.3 microseconds.