DocumentCode
2316641
Title
Buffer allocation for advanced packet segmentation in Network Processors
Author
Llorente, Daniel ; Karras, Kimon ; Wild, Thomas ; Herkersdorf, Andreas
Author_Institution
Lehrstuhl fur Integrierte Syst., Tech. Univ. Munchen, Munich
fYear
2008
fDate
2-4 July 2008
Firstpage
221
Lastpage
226
Abstract
In current network processors, incoming variable-length packets are sliced using only one small segment size and then stored in the buffer. Inconveniently, short data bursts are inadequate for accessing SDRAM, commonly used for packet buffers, due to high activation and pre-charging latencies. Using large segment sizes is not optimal either because though it increases memory bandwidth, the benefit comes at the price of a heavy reduction in storing efficiency. A good solution to achieve simultaneously high performance and memory utilization consists in storing a single packet segmented using multiple segment sizes. In this paper, we study how to allocate memory for these different-sized segments in an efficient way. First we analyze the appropriate segment pool size for a multitude of traffic scenarios. Our experiments show that simple static buffer allocation does not always suffice as different segment pools may be exhausted depending on traffic. Hence we introduce a method for handling multiple segment pools not only in a static but also in a dynamic way, taking advantage of a new set of control structures based on a combination of bitmaps and linked lists. We demonstrate that our method achieves a huge reduction in control buffer size requirements in comparison to state-of-the-art control structures, together with decreasing the average number of accesses to control data.
Keywords
DRAM chips; buffer storage; SDRAM; advanced packet segmentation; buffer allocation; memory utilization; network processors; traffic scenarios; Application specific processors; Bandwidth; Buffer storage; Delay; Information retrieval; Memory management; SDRAM; Size control; Throughput; Traffic control; Buffer Management; Dynamic Memory Allocation; Memory Subsystem; Network Processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on
Conference_Location
Leuven
ISSN
2160-0511
Print_ISBN
978-1-4244-1897-8
Electronic_ISBN
2160-0511
Type
conf
DOI
10.1109/ASAP.2008.4580182
Filename
4580182
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