DocumentCode :
2316831
Title :
Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing
Author :
Chen, Tse-Wei ; Ikeda, Makoto
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan
fYear :
2012
fDate :
18-20 April 2012
Firstpage :
1
Lastpage :
3
Abstract :
Different from previous works that focus on the iterative clustering algorithm, a dual-stage hardware architecture that supports two kinds of moving averages for the on-line clustering algorithm is proposed. The architecture includes a set of memories that operates in ping-pong mode, so that distance computations and centroid updating can be processed in pipeline. The high-throughput parallel divider in the moving-average engine is a new solution to reduce the overhead of divisions to only 1 clock cycle and to calculate cumulative moving averages with no precision loss. The experiments show that when the operating frequency is 400MHz, the gate count and the average power consumption are 16K and 6.02mW, respectively. The normalized power consumption of this work is the lowest among previous works.
Keywords :
logic design; moving average processes; signal processing; centroid updating; distance computation; dual-stage hardware architecture; frequency 400 MHz; gate count; high-throughput parallel divider; iterative clustering algorithm; low-power signal processing; moving-average engine; online clustering; ping-pong mode; power 6.02 mW; power consumption; Algorithm design and analysis; Clustering algorithms; Computer architecture; Engines; Hardware; Signal processing algorithms; Vectors; Architectural analysis; digital circuits; logic design; machine learning; signal processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Cool Chips XV (COOL Chips), 2012 IEEE
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-1201-1
Electronic_ISBN :
978-1-4673-1200-4
Type :
conf
DOI :
10.1109/COOLChips.2012.6216580
Filename :
6216580
Link To Document :
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