Clock skew reduction approach for standard cell

Author

Saigo, Takashi ; Watanabe, Seiji ; Ichikawa, Yoshihiro ; Takayama, Shin´ichi ; Umetsu, Tsutomu ; Mima, Kenji ; Yamamoto, Tadahiko ; Santos, Joe ; Buurma, Jake

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

13-16 May 1990

Abstract

Five clock treatments are evaluated by SPICE simulation. The wide trunk-line with balanced output short sub-buffering scheme is the best way to reduce the clock skew and delay. In order to realize this scheme, a special clock treatment has been developed. This includes insertion of sub-buffers, regeneration of channel relation trees and special global routing. Maximum clock delay and skew are simulated to be 3.6 ns and 1.4 ns respectively under the condition of 2000 fanouts and 15-mm-square die size on 1.0 μm design rule. This approach will be available on both TC24SC (1.0 μm) and TC25SC (0.8 μm) standard cell

Keywords

cellular arrays; circuit layout CAD; clocks; digital integrated circuits; 1 micron; 1.4 ns; 15 mm; 3.6 ns; SPICE simulation; TC24SC; TC25SC; balanced output short sub-buffering scheme; clock delay; clock skew reduction approach; clock treatments; design rule; die size; fanouts; global routing; insertion of sub-buffers; placement and routing; regeneration of channel relation trees; standard cell arrays; wide trunk-line; Application specific integrated circuits; Clocks; Delay effects; Joining processes; Large scale integration; Microelectronics; Propagation delay; Rivers; Routing; Systems engineering and theory;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124753

Filename

124753