Title :
DHT: diagonally hybridized tree is an efficient VLSI structure for parallel computation
Author_Institution :
Comput. Center, Banaras Hindu Univ., Varanasi, India
Abstract :
A new tree-based VLSI architecture called a diagonally hybridized tree (DHT) is proposed. DHT requires less hardware in terms of number of processors, connecting links and layout area compared to a mesh-of-tree of comparable size. By mapping a number of representative problems on DHT, the suitability of DHT for parallel computation is demonstrated. The results show that DHT with a sequential host can be used as a general-purpose parallel computer. A scheme is also given to tolerate faults in DHT by using spare processing elements (PEs) and links. It is shown that, asymptotically, DHT can tolerate O(N) faults by using O(N) spare PEs and O(N ) spare links
Keywords :
VLSI; fault tolerant computing; parallel architectures; trees (mathematics); VLSI architecture; diagonally hybridized tree; fault tolerance; general-purpose parallel computer; parallel algorithms; parallel computation; processing elements; sequential host; Algorithm design and analysis; Computational modeling; Computer architecture; Concurrent computing; Fault tolerance; Parallel algorithms; Parallel processing; Routing; Tree graphs; Very large scale integration;
Conference_Titel :
Computer and Communication Systems, 1990. IEEE TENCON'90., 1990 IEEE Region 10 Conference on
Print_ISBN :
0-87942-556-3
DOI :
10.1109/TENCON.1990.152662
