Title :
A flexible multi-port RAM compiler for datapath
Author :
Shinohara, Hirofumi ; Matsumoto, Noriaki ; Fujimori, Kumiko ; Kato, Shuichi
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kbit) and 10.0 ns (32 kbit), for example
Keywords :
CMOS integrated circuits; SRAM chips; VLSI; cellular arrays; circuit layout CAD; integrated circuit technology; integrated memory circuits; 1 micron; 1 to 32 kbit; 10 ns; 5 ns; CMOS; additional column enable gate; address access times; flexible layout; floorplan; memory cell scheme; multiport RAM compiler; port-organization; six-port RAM; three-port RAM; CMOS technology; Circuits; Delay lines; Laboratories; Large scale integration; Random access memory; Read-write memory; Research and development; Throughput; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124754
