Title :
A high performance one micron CMOS technology chip
Author :
Melrose, Caryn ; Klein, Guenter ; Feng, Eugene
Author_Institution :
IBM Corp., San Jose, CA, USA
Abstract :
A high-performance, semicustom, 9.44 mm×9.35 mm chip built on one micron CMOS with two levels of metal is described. Pulse distortion and delay were the limiting design factors. A practical limit of 96 MHz was specified on all critical nets due to pulse distortion. Custom macros were designed and used in critical areas to limit pulse distortion and to meet tight delay tolerance specifications. Wiring capacitance was specified to be limited to 0.5 pF/fanout with a maximum of three fanouts per output stage. Only logic books having buffered output stages were used in critical nets. Capacitive loading constraints required manual intervention in the placement and wiring process
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; circuit layout CAD; integrated logic circuits; 1 micron; 9.44 mm; 96 MHz; CMOS technology chip; capacitive loading constraints; critical areas; critical nets; delay tolerance specifications; limiting design factors; logic books having buffered output stages; manual intervention; placement and wiring process; pulse delay; pulse distortion; semicustom; two level metal; wiring capacitance; CMOS technology; Capacitance; Circuit testing; Delay; Integrated circuit noise; Logic design; Noise reduction; Pulse circuits; Space vector pulse width modulation; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124755
