Title :
An ADVANCELL 1.0 mainframe chipset-2.2 million transistors on 11 ICs
Author :
Schrader, Lothar ; Haff, Norbert ; Weller, Artur
Author_Institution :
Siemens AG, Munich, West Germany
Abstract :
A CMOS mainframe chipset of 11 VLSI ICs and a total of 2.2 million transistors aiming at the computing power of previous ECL machines has been developed. The IC design and layout was done by means of proprietary CAD systems using the ADVANCELL 1.0 cell library and high-performance support cells, as well as a special packaging technique. A hierarchical cell-based design methodology was applied by using Siemens tools for schematic capture and layout (VENUS) and a proprietary simulation and verification environment from chip- to system-level (PRIMUS), including automatic test pattern generation, testability rule-checking, and fault simulation
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; circuit layout CAD; packaging; ADVANCELL; CMOS; PRIMUS; Siemens tools; VENUS; VLSI ICs; automatic test pattern generation; cell library; computing power; fault simulation; hierarchical cell-based design methodology; high-performance support cells; mainframe chipset; packaging technique; schematic capture; testability rule-checking; verification environment; Automatic test pattern generation; Design automation; Design methodology; Integrated circuit layout; Integrated circuit packaging; Libraries; Packaging machines; Transistors; Venus; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124756
