Title :
Synthesis of self-timed circuits without state assignment
Author :
Chia, Wei-Kuo ; Kuo, Yau-Hwang
Author_Institution :
Inst. of Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Based on the work of T.A. Chu (1986) and T.H. Meng (1989), the authors develop a new deterministic synthesis algorithm that directly synthesizes a self-timed circuit from an STG by means of dynamic behavior analysis. An STG model is used to describe circuit behavior as discussed by Chu and Meng. The self-timed circuit is an asynchronous circuit scheme whose circuit behavior is speed-independent or delay-insensitive, that is the circuit behavior is independent of the delay of the constituent physical components
Keywords :
network synthesis; timing circuits; STG model; VLSI; asynchronous circuit; deterministic synthesis algorithm; dynamic behavior analysis; network synthesis; self-timed circuits; strongly connected graph; Algorithm design and analysis; Circuit synthesis; Clocks; Delay; Design engineering; Signal design; Signal synthesis; Synchronization; Very large scale integration; Wire;
Conference_Titel :
Computer and Communication Systems, 1990. IEEE TENCON'90., 1990 IEEE Region 10 Conference on
Print_ISBN :
0-87942-556-3
DOI :
10.1109/TENCON.1990.152665
